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Implementation And Verification Of Static Image Compression Algorithm Based On FPGA

Posted on:2015-03-03Degree:MasterType:Thesis
Country:ChinaCandidate:X G LiFull Text:PDF
GTID:2308330464464672Subject:Physical Electronics
Abstract/Summary:PDF Full Text Request
With the development of information technology, the demand for data is growing more and more urgent. Image data is the most common form of data, and its vast amount of data bring huge challenges to system transmission and storage. Therefore, the image compression technology has been widely applied and developed. And the image compression methods based on software have become more and more difficult to meet the actual demand because of the increasing real-time requirements for some applications. FPGA is now playing an increasing important role in the field of image compression in hardware for its high-speed, parallel computing characteristics and unsurpassed design flexibility of ASIC.This paper studies the implementation and validation of the static image compression algorithm based on FPGA, introduces the basic principles of JPEG standard, the algorithm and implementation method of the JPEG basic system. According to the algorithm of JPEG image compression, the system consists of four modules,1D-DCT module,2D-DCT module, quantization and Zig-Zag scanning module and entropy coding module.1D-DCT module is designed by AAN algorithm, which takes 6 clock cycles, including 29 additions and 5 multiplications, supports continuous data input and output, meets the requirement of real-time computing by using pipeline structure. 2D-DCT module is designed with 21D-DCT modules and 1 storage module, which is implemented with ping-pang operation to realize the real-time data cache.Quantization and Zig-Zag scanning module quantizes and scans the DCT result to get DC and AC coefficients. Entropy coding module encodes DC and AC coefficient by DPCM and RLE, followed by huffinan coding.In this paper, each module is verified with Matlab, designed on FPGA and simulated with Modelsim software. The hardware test platform is bulit, and transmits result data to the host PC by USB2.0 interface. The core device of hardware test platform is EP3C16F484I7 of Altera Corporation, and the software used is Matlab2011a, Quartus Ⅱ12.0 and Modelsim 10.0c.The simulating and testing results show that the JPEG image compression system is stable and correct at 100Mhz with the compression rate of 4.92, which meets the design requirements.
Keywords/Search Tags:JPEG, 2D-DCT, Entropy Coding, FPGA, USB2.0
PDF Full Text Request
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