Design Of High-performance JPEG Encoder Based On HLS

With the advancement of integrated circuit technology,it is easier than ever to design a dedicated hardware circuit for JPEG encoding.The hardware-based JPEG encoding circuit has the advantages of higher efficiency,lower power consumption,and higher parallelism than software algorithms.However,there are still huge difficulties in designing hardware circuits using traditional methods.The continuous development and progress of high-level synthesis technology makes it a viable option for designing hardware-based circuits.The algorithm-level code is used to automatically build register transfer-level files that meet the constraints.The optimized high-level synthesis design can be converted into a low-latency and high-throughput circuit,so it is of great significance to design JPEG encoder circuits using high-level synthesis technology.This paper uses HLS to design the JPEG encoder.Aiming at the problems of high latency and low encoding throughput of traditional JPEG encoder,the design of JPEG encoder with optimized structure and performance is proposed.In optimizing the structure of the JPEG encoder:the column dct,quantization and zigzag modules with the same bit width and rate are combined to reduce the interface circuit area.The zero-nonzero searching,huffman encode and writebits modules in entropy coding with different bit widths and rates are splited into three modules,and use FIFO circuits to connect them,which greatly reduces the coding latency;in terms of performance optimization:using loop unrolling,pipeline and function division methods optimized the JPEG encoder's DCT,quant,zigzag and entropy encoding modules.The optimized design effectively reduces the latency and improves the throughput.After simulation testing,the RTL code function of the JPEG encoder is completely consistent with the HLS program.The latency cycle of the JPEG encoder is 24,and the coding efficiency is 14.41 clock cycles/block.Compared with the conventional structure JPEG encoder designed by the traditional method,the design proposed in this paper reduces the latency by 74%and the encoding efficiency by 85.27%.In view of the problem of circuit power consumption and large area caused by the adoption of HLS,this paper uses gated clock enable signal generation,FSM coding and idle signal insertion to optimize the power consumption of JPEG encoder,using operands Methods such as aggregation,resource sharing,and removal of redundant logic optimize the area of the JPEG encoder.The test results show that the power consumption of the JPEG encoder is reduced by 20.3%after optimization,and the area is reduced by 11%after optimization.