Research And Design Of Millimeter Wave PLL And Accurate Quadrature Clock Generator Based On CMOS

With the growing needs of information communication, short-range high speed wireless communication based on millimeter-wave and internet communication technology based on fiber are extensively researched at home and aboard. Meanwhile the rapid progress in CMOS technology makes it possible to transfer integrated circuits for millimeter-wave and optical communication from traditional Ⅲ-Ⅴ compound semiconductor to inexpensive silicon-based technologies. On one hand, there is an insatiable need for wide tuning range and low phase noise oscillator in millimeter wave communication. On the other hand, ultra high speed time-interleaved ADC used in optical communication also puts forward high requirements for multiphase sampling clock. Therefore, the main research contents of this work is 60GHz millimeter-wave PLL and accurate multi-phase clock generation circuit for ultra-high speed ADC.First, the basic principles and design methodology of PLL is presented and a design procedure based on loop stability was summarized. After that we go for the circuits designs of 60GHz PLL and quadrature clock generation in details, which mainly include subjects as follows:(1) A wide tuning range millimeter-wave VCO based on tunable inductor loads is proposed. The resonant frequency can be adjusted by switching the secondary coil of the transformer load. Besides, the VCO’s output is coupled through the transformer to the next ILFD, which can benefit both VCO’s resonant frequency and the injection efficiency. As a result, the locking range for ILFD is widened. The VCO designed in this work can cover 60-67GHz with more than 11% tuning range and the ILFD has achieved 54-71 GHz for input locking range under OdBm input.(2) Based upon the wide tuning range VCO and ILFD, a 60GHz PLL is realized, which also includes regenerative frequency dividers, CML dividers, programmable frequency dividers, PFD and CP.(3) A wideband quadrature ILFD with tunable output phase is proposed, which is achieved by turning the bias of injection and coupling signal. In this way, the output phase mismatch caused by PVT variation could be ameliorated. The post simulation shows that the ILFD has a locking range of 9-20GHz and the average absolute phase error is less than 0.26°(4) A quadrature PLL applied for time-interleaved ADC is proposed and realized based on the ILFD mentioned above. It covers a frequency range of 5.8-6.5GHz and 7.1-8.3GHz, which meets the application requirements. The VCO and ILFD have a phase noise of -105dBc/Hz at 1-MHz offset.(5) Both designs are fabricated in TSMC 65nm CMOS progress, which are currently under testing.