Reed-Solomon Code Implementation With FPGA In Optical Record Systems

Error-correction coding can improve the communication reliability by inserting redundancy into message sequence while decreasing information transmission rate. Reed-Solomon (RS) code is one of nonbinary cyclic codes, which has strong error-correcting capability for burst errors. With the development of efficient decoding algorithm and large scale integrated circuit technology, RS codes have been widely applied in many fields, such as deep space communication, mobile communication, military communication, optical fiber communication, digital video broadcasting sysemts, magnetic or optical record systems.With the great development of microelectronic technology and process level, using Field Programmable Gate Array (FPGA) devices, we can design complicated digital circuits effectively, which shortens the designing period and decreases the implementation complexity, compared with Application Specific Intergrated Circuits (ASIC) devices.This thesis focuses on the encoding and decoding principles of RS code and the FPGA implementation of the encoder and decoder of RS (208,192) code in the optical record DVD system from GB/Z 18808-2002 standard. The main contents can be summarized as follows:1,Based on the history of error control codes and the optical record system, the principle and data structure of the Digital Versatile Disc (DVD) system and the application of RS code in the DVD system are introduced;The fundamentals of RS code, including the basic algebra theory, the process of addition,multiplication,inversion in the finite field are studied;On the FPGA platform, in terms of the logical operation way, three methods are proposed to realize RS encoder, which are general multiplier, constant multiplier and constant adder, respectively. And the hardware resource efficiency using these three methods are analyzed, and a conclusion is made that general multiplier has the highest logical complexity;The decoding procedures of RS code are analyzed, by dividing the RS decoder into five modules, which are syndrome computation module, error position polynomial computation module, error position computation module, error value computation module and shift register module.2,In order to avoid the inversion operation in finite field and reduce the decoder complexity, modified Berlekamp-Massey (BM) iterative decoding algorithm is derived, which can convert the division operation into multiplication operation;In order to avoid the multiple exponential operation, the iterative algorithm is applied in the error positon computation module and error computation module. The exponential operation is transformed into the constant multiplication operation, which is excuted only once in each clock.3,The circuit diagrams, simulation waveforms and hardware resource utilitaion rate are got in the FPGA simulation. The results indicate that the modified BM algorithm can reduce the operation complexity effectively and only 4514 logical cells are used. Moreover, the iterative algorithm can improve the opreation rate and the clock frequency can achieve 99MHz.