Study On Reed-Solomon Decoder And Its Implementation In FPGA

RS(Reed-Solomon)code is a kind of nonbinary BCH code. Because of its structure it can correct not only random errors but also outburst errors. So it is widely used in many communication systems and digital storage equipment, for examples deep-space communication, optical fiber communication,hard disk array, DRAM,CD etc.This article introduced basic theory of error-correcting code, the decoder algorithm of RS code and its implementation in FPGA.Main work in this paper: 1)using verilog language describe how to encoding and decoding RS code including the Galoias multiplier, Syndrome circuit, Berlekamp arithmetic circuit, Qian search circuit and UART circuit.2) using CMOS chip EP1C6Q240C8 of ALTERA's Cyclone as the hardware implement RS decoder and reaches the anticipative performance.Because of using RS(255,239) code it can correct 8 errors. Using Cyclone chip implement the decoder can ensure the speed and keep its strong correction ability at the same time.