Design And FPGA Implementation Of FEC Code For High-Speed Optical Transport System

Problems such as bit error rate rising due to OSNR worsening in beyond-100 G optical network can be overcome by utilizing FEC codes which are comprehensively applied among optical networks.Traditional encoders with high latency cannot meet the requirements of highspeed optical network,and studies on high-speed RS encoder are rare.Studies on RS decoders usually focus on key equation solving algorithms rather than low latency decoding schemes.On the other hand,polar codes,which was brought out recent years,can achieve channel capacity theoretically,thus capturing attention comprehensively.Polar codes have been developing rapidly and also been studied popularly for next generation forward error correction.Aiming to tackle those problems mentioned above,the following studies were carried out:(1)An ensemble of parallel encoding and decoding scheme was proposed and implemented with FPGA for KP4-FEC,i.e.RS(544,514)code,for 100GE/400 GE Ethernet interface with the encoder's throughput reaching above 17 Gb/s,and latency of 0.14 ,while the decoder's throughput reaching above 66 Gb/s,and latency of 0.17 .Both the encoder and the decoder are capable for the demands of high-speed optical network nowadays.(2)Encoding and decoding methods for polar codes were introduced,and three concatenation schemes of RS-polar codes are brought out for future flexible optical network: two fixed-rate concatenated codes and a flexible code with 2-D frame structure.The former two codes are suitable for low SNR and high error rate scenarios.The third one can change information and overhead rate flexibly to cope with heterogeneous SNR conditions and meet the error correction performance demands.(3)Joint decoding schemes have been developed,including:(1)Fast joint decoding algorithm;(2)Iterative joint decoding algorithm.The former is for high SNR,low overhead applications,where decoding polar codes is omitted when RS codes have no error.The latter considers the 2-D frame structure of concatenated code as a whole,and improve error correction performance by taking advantage of the interaction between inner and outer codes,thus reducing decision error probability of SC decoding,obtaining further concatenation gain.FEC codes for high speed optical transport network were studied in this thesis,and the RS code for beyond 100 Gbit/s network was implemented with FPGA.Concatenating scheme of polar codes and RS codes and corresponding joint decoding performance were studied for fundamental works of utilizing polar codes in the future.And applications of RS-polar concatenation codes among next generation optical networks were also explored.