Research And Design Of H.264/AVC-based Video Decoder

With the development of digital storage, multimedia communication and computer technology, the demand of high-definition digital video is growing. In order to meet a series of requirements including video quality, transmission speed and real-time processing capability, highly efficient video compression standard and high performance video decoder research also develops rapidly. H.264/AVC video standard promulgated since 2003, it has been widely favored by market users for its highly efficient compression performance and superior network compatibility. Therefore, the hardware implement of the standard has great significance.In this paper, we choose the basic grade decoder of H.264/AVC standard as a research object. The principles of H.264/AVC codec algorithm is studied deeply and H.264/AVC video decoder is designed by using a parallel pipeline plan in this paper. This paper presents the macro block level H.264/AVC video decoder structure which supports a variety of formats video decoder. This paper specifically includes:(1) CAVLC and IQIT. After researching the decoding algorithm of H.264/AVC standard, we use the FSM (Finite State Machine) to control the timing of CAVLC module and use the reusable butterfly transformation to achieve inverse transform inverse quantization design, which reduce the system resource consumption.(2) Intra prediction. After analyzing the intra decoding algorithm of H.264/AVC, we extract the general characters of different modes’algorithms. A basic arithmetic unit is devised to fulfill predicted pixel’s calculation when calculating the predicated value of pixels. Splitting calculation module method is designed to complete the calculation for the more complicated Plane-mode. This method effectively save system resources and improve the decoding speed.(3) Inter prediction. According to the inter prediction model and decoding algorithm, Luma interpolation works on 4 X 4 block base and Chroma interpolation happens on 2 X 2 block base, which are processed parallel and used different interpolation optimization design. When fetching the reference pixels for different interpolation, it used a self-adapt block shape method to effectively reduce the external memory access number and improve the decoding speed.(4) Deblocking filter. This paper proposed a new filtering order and reasonable allocate memory resources, after analyzing the algorithm of loop filter. The pixel filter and pixel transfer works in parallel. This method accelerates the loop filter speed.This paper constructed the hardware structure and realized the design of each module with Verilog HDL language, simulated each module in ModelSim. The system function had been verified by comparing the results using hardware decoding designed with that using JM software. Then fullfilled the functional simulation, system synthesis and FPGA verification board. The result of verification shows that the design can support real-time decoding with H.264/AVC basic profile video sequences.