The Research And Design Of Critical Algorithms In Video Codec Based On FPGA

As a mature video compression coding standard, H.264/AVC is now widely used in video surveillance, digital TV, high-definition video and other fields. H.264/AVC has a high compression ratio and a nice affinity for network, but the computational complexity increased a lot while obtain a high compression ratio. The computational complexity of H.264/AVC standard is 2.5 times than the previous generation of video coding standard H.263, which brings a test for processor’s computational ability. The new generation of video coding standard H.265/HEVC has a higher compression ratio than H.264/AVC, and needs a strong computational ability to achieve real-time video codec. Considering that FPGA have some features such as fast processing speed, parallel processing, taking IP flexibly, this paper do research and design of some critical algorithms in H.264/AVC codec and H.265/HEVC codec based on FPGA.This paper explain the theory of H.264/AVC standard, focus on analyze intra prediction algorithm, IQIT algorithm and deblocking filter algorithm of H.264/AVC decoder. Optimizing intra prediction algorithm of H.264/AVC by using adaptive pipeline processing and 4-channel paralleled PE to calculate 4 pixels’values within a period. Design two reconfigurable computing units for IDCT and inverse quantization. Propose an optimized filter order for deblocking filter algorithm thus enhance the data reuse greatly while filtering, using pipeline structure to achieve the computing process. Abstract some critical variates from official coding model JM and compare with the RTL simulation results of intra prediction algorithm’s hardware, IQIT algorithm’s hardware and deblocking filter algorithm’s hardware of H.264/AVC that designed, which proved the correctness of the designed algorithm’s hardware. Achieve the design of hardware circuits based on EP4CE115F29C7 development platform of Altera company, and the result shows:the supported resolution and frame rate of intra prediction hardware circuits, IQIT hardware circuits, deblocking hardware circuits are 1920×1080@42fps,1920×1080@60fps, 1920×1080@60fps respectively, gaining a great real-time performance.Introduce the coding framework of H.265/HEVC and analyze intra prediction algorithm in detail. Adopt 64-channel paralleled PE cooperate with control unit and pixel access to achieve the intra prediction’s mode selection of a LCU block. Avoid some difficulties of hardware design caused by various block size after doing all mode traversal in order of small block to big block. Adopt 16-channel paralleled way to calculate 16 pixels’prediction values of a 4×4 block within a period. Achieve the hardware design of H.265/HEVC intra prediction algorithm and put forward a completed storage design, the new mechanism can save amounts of memorizers.