Study On Algorithms And Implementations Based On H.264 Baseline Profile

With the development of communication technique and micro-electronic technique, it is the trend to provide video services for hand-hold mobile terminals. Limited by the memory and channel bandwidth, the digital image signal must be compressed. The H.264/AVC standard, raised by the JVT of ITU-T/VCEG and ISO/IEC/MPEG, is a good selection to this application. The H.264/AVC standard has good compression performance and friendship with different channels and so it is widely used. The baseline profile within the H.264/AVC standard is suitable for the application to hand-hold mobile terminals. This thesis focuses on the baseline profile, including the relative algorithms and real-time hardware implementations.At first, the architecture of video codec with advanced DMA bus is proposed, according to algorithms in the baseline profile and system design specification. The codec has simple external interface and can be easily integrated in different systems. By the limited pipeline technique, the codec meets the real-time requirement and saves the buffer between stages. The codec can work under these modes: digital camera, digital video, video phone, and video broadcast owing to the dedicated design of the system state machine.And then this thesis researches the optimization of the algorithms and the corresponsive hardware implementations within the baseline profile. In the prediction field, the principles of the intra prediction and inter prediction are analyzed. The creative work includes mainly: (1) the proposed selection methods of intra prediction modes, which are easily implemented by hardware; (2) the proposed intra codec architecture with decoding and encoding hardware reused, with five stage pipelines for speedup and with reconfigurable intra processor for 17 prediction modes; (3) the proposed high speed motion estimation algorithm, called as the butterfly-shaped search algorithm; (4) the hardware implementation of butterfly-shaped search algorithm, which solves the difficult problem of the hardware implementation of one class fast motion estimation algorithms. In this field, the thesis also works on the analysis of algorithm and special hardware implementation of the fractional motion estimation and compensation. In the transform field, based on the understanding of the integer DCT/IDCT and Q/IQ, this thesis proposed the relative hardware architecture. The advanced application-the detection of all-zero blocks is discussed in this field. The proposed CAVLC/CAVLD hardware architecture is described in the entropy coding field based on the analysis of their principles. In reconstruction field, this thesis focuses on the implementation of the deblocking filter. One block-based hardware architecture is proposed. Because the input data character from the former module has been considered, this architecture achieves faster process speed than other similar architecture.At last, the simulation under MATLAB platform and the verification under the Xilinx's Virtexâ…¡Pro FPGA-based development system show that the proposed video codec meet the design specification.