Research On Modeling For RF CMOS Transistor Technology

Driven by the rapid development in the fields of the internet and integrated circuits in recent years,cell phones,computers and other consumer electronics products are being replaced at an increasingly rapid rate,and users’ demand for higher performance of electronic devices has led to an increasing demand for integrated circuit chips.A common technology in the semiconductor industry and the go to option for integrated circuit design,CMOS technology has a number of benefits for integrated circuits,including cheap cost,low power consumption,a straightforward manufacturing process,and simplicity of large-scale integration.The density of transistors per unit area,along with the size of the components,are all increasing as the scaledown of integrated circuit.As CMOS devices are getting smaller,certain new issues also arise as a result.The reduction in device feature size increases its cutoff frequency,and small sizes bring about more complex physical effects and parasitic effects at high frequencies.Accurate transistor models can improve the accuracy and efficiency of circuit design,reduce chip development cycles and costs.Therefore,these effects need to be accurately described in transistor models.This thesis investigates the relevant models for RF transistors based on 65 nm CMOS LP technology.First,the background of MOSFET model research,the current state of research on MOSFET device models,and the significance of MOSFET device models in integrated circuit design are explained in this thesis.It also goes into detail on the device structure,working principles,and common physical effects of MOSFET devices,as well as a thorough introduction to the frequently used small variant,BSIM4.Furthermore,to obtain the measurement data for modeling,an accurate characterization of the embedded model of the test structure is performed.To get rid of the parasitic parameters brought on by the test structure,a novel open-short de-embedding technique is applied.Based on the measurement results,a small-signal equivalent circuit model of the MOSFET is created in accordance with the transistor’s physical composition.The model parameters are then extracted to confirm the accuracy of small-signal model.The model’s relative root-meansquare error is less than 5%.Subsequently,the BSIM4 model was studied and improved based on the established small-signal equivalent circuit model,considering a more complete substrate parasitic network to construct a large-signal model of the MOSFET.To better explain the nonlinear DC features,the BSIM4 DC model parameters were extracted and adjusted based on DC measurement data.The DC model’s relative root-mean-square error is within 7%.The model can more accurately depict the RF properties of the transistor under various biases in the range of 0.1 GHz to 50 GHz when validating the small-signal S-parameters.Finally,verification of the large-signal model was achieved through power-sweep and load-pull tests,with the results demonstrating its high accuracy in terms of output power,power gain,power added efficiency,and load-pull.