| With the development of semiconductor to deep submicron and advance node,the effect of Layout Dependent Effects(LDE)on device characteristics is becoming increasingly prominent.In the design process,the simulation results must correctly reflect the influence of LDE in the circuit.Well Proximity Effect(WPE)is one very important part of LDE.In BSIM model,the equation of calculating relative instance parameters of well-proximity effect is very complex.Due to the limitation of EDA tools,the calculating equation may be simplified,resulting in errors in pre-simulation at the beginning stage of design.In order to reduce the errors in the pre-simulation to accelerate design convergence,this paper present the method to improve the accuracy of the well proximity effect in the pre-simulation.The main research work and achievements have been completed:1.Based on 28 nm CMOS process,the well proximity effect was studied.The parameters of well proximity effects,including the MOSFET channel length,channel width,Fingers and space between MOSFET channel and well edges,which would affect result are analyzed by simulation and experiments.2.According to equations of WPE model,the optimized formulas of calculating instance parameters that represent the integral of the first/second/third distribution function for scattered well dopant are delivered and verified.It's because the original equations are too complex to be calculated accurately by EDA tool in traditional flow.3.The simulation method of well-proximity effect in the traditional design process is studied.Based on simulations and tests,the causes of pre-simulation errors in design are analyzed from two aspects of process design kit and EDA.In this paper,by optimizing the process suite to transfer the parameters of well-proximity effect in simulation,and combining with the optimized model parameter equation,a new simulation method for well-proximity effect is realized,which avoids the limitation of EDA tools and effectively transfers the simulation parameters directly to the MOSFET SPICE model to improve the accuracy of simulation result.Based on the 28 nm process design kit,we created the test circuit to run simulation for verifying the new method.The simulation data shows that the error ratio is reduced from 7% to 0.01% and simulation results are more accurate and reliable than before. |
