Design And Implementation Of A 16-bit RISC Processor On FPGA

Reduced Instruction Set Computer (RISC) is a novel idea of microprocessor design that was firstly proposed in the 1980s. Its features are that selects the most frequently used instructions in priority, and the format of instructions is regular, the addressing mode of instructions decreases. So the time of instructions decode stage will be shortened, and the pipeline can flow smoothly. Due to the advantages of simplification and high efficiency for RISC processor, RISC processor has been paid extensive attention in the industry since it was put forward. At present in high-performance server and embedded field, ninety percent of the processors are designed based on RISC architecture t. However, in the classic five-stage pipeline architecture of RISC processor, there is a large deal of logic, which may lead to congestion, and thus affect the execution velocity of the pipeline. In order to avoid the occurrence of logic congestion, further improve the speed of data processing and extend the function of the processor, the structure of the pipeline will be re-divided in this dissertation, and a new design of the five-stage pipeline was proposed. The pipeline structure consists of the instruction fetch unit, decode unit, the front-end logic execution unit, arithmetic execution unit and register access unit. In the arithmetic execution unit, we added a new multiplier-accumulator to expand the function of the RISC processor. Compared with ordinary multiplier-accumulator, the new multiplier-accumulator paid attention to the circuit structure, and its execution speed increased three times. The dissertation analyzed the structure-relativity, data-relativity and control-relativity introduced by the pipeline, then used the Harvard architecture and the internal forwarding to solve the structure-relativity and data-relativity respectively in the pipeline. At the same time, the method of software programming was used to solve the control-relativity of the pipeline to ensure the efficiency of the pipeline.In this dissertation, Verilog HDL was applied to describe the processor system in the implementation stage. Then functional simulation of five levels and overall structure is carried out by simulation software-Modelsim, and the synthesis and static timing analysis are executed by the software-Quartus Ⅱ. The results from simulation and synthesis can be seen:each instruction in the pipeline can be accomplished in a single clock cycle, and the processor can execute smoothly and quickly. Timing reports show that any timing violations do not occur in the processor, which meets the requirements of timing design, and the maximum frequency of the five-stage pipeline is up to 172.95MHz. At last, through building hardware test system around the microprocessor, and verifying on FPGA board, the design achieves the expected goal.