Soft-core Risc Microcontroller Design, Based On The Pipeline Processing

In this paper, an 8-bit micro-controller soft core was designed inVHDL language with top-down design method.A new RISC instruction set which length is 24-bit was designedfor the micro-controller, the first byte of which is operation code that the function and mnemonic is the same to MCS-51, the secondand third byte is operation data. The instruction set is compatiblewith the 111 instructions of MCS-51.The microcontroUer includes 216-bit calculagraph-arithmometer, a full duplex UART ports,5 interruption sources with 2-level interruption priority, high and low 128 byte RAM, all of these modules are compatible with that of MCS-51. Furthermore, hardware watch dog, software reset, registers transmitting data-directly and other functions are designed for the microcontroller. In order to improve the convenience in embedded application, the implement of division module and multiplication module can beopted,the system clock too.3-1evel instruction pipeline was usedin the microcontroller, all the instruction can be done in one clockon condition that with no conflict exclude MOVC instruction. Thesystem clock frequency was improved by optimizing the structureof pipeline. Direct-connect structure was designed, so special function registers connect with other modules directly, with that the system efficiency was improved.The microcontroller core, Source codes of all the modules of whichwere write in ISE soft environment,was synthesized with Synplifypro8.0,and simulated by ModelSim 6.0D with function simulation andtiming simulation, downloaded and ran in FPGA .The core achieved allthe design targets on soft and hard verification at present.The microcontroller core is compatible with MCS-51 well, theefficiency and executing speed of the instructions of which is very high, and the configure of the system is flexible, all of these could meet thedemand of embedded microcontroller application. The accomplishmentof this microcontroller can settle a strong base to design other ASICs andimplement system integration.