Mcs8051 And Ds80c320 Microcontroller Soft Core

Two 8051 serial soft IP COREs validated successfully by FPGA chip are introduced in this paper. The first one is 80C51 MCU IP CORE designed by VHDL, and the second is DS80C320 MCU IP CORE designed by Verilog; In this paper the functional structure of 8051MCU is introduced first. Then we discuss the real structure used in this design. And also the advantage of the real structure about fitting FPGA design will be pointed out. In the forth chapter, the real flow and timing of instruction inside will be introduced to understand all the function modules in design. then we discuss the DS80C320 IP CORE, the emphases lies in the difference to 8051MCU,such as timer II and the buildup UART. Finally we show the testing and summarize. The principle of design is the user handbook and official data about this MCU. By using black box theory the design has much improve in performance based on compatibility. For example, the speed of 8051 MCU increases from original 12M to 62.5M and the DS80C320's speed increases from 33M to 73M. The application of soft IP CORE makes the design to be used in both FPGA chip and ASIC technology. At the same time, as soft IP CORE, this design can be used as a single application or a module of other design. This design uses the QUARTUS II 4.0 software of Altera Inc to synthesize, place, route, map and download the design to FPGA chip, uses the modelsim 5.8 to test the simulation of design, uses the EP1C20F400C6 chip of Altera Inc's cyclone serial to finish the physical test, uses the 1673G logic analysis of Agilent Inc to finish the physical timing test. This design uses the top-to-down and module ways to decrease the design period and cost compared to the tradition way. The advanced technology can also ensure the improvement of performance.