| The requirements of the people’s life drive many wireless communication standards to be published. The second generation and the third generation wireless mobile communication systems rely on basestations so that they could not be applied in earthquake areas such as GSM and W-CDMA, and communication distance of the existing wireless peer to peer communication systems is not enough to organize a large-scale wireless self-organization network such as Bluetooth and WLAN. In order to facilitate the people’s life, it is significant to design a transceiver which could merge the existing wireless communication standards and support long-distance wireless peer to peer communication. As the lower carrier frequency could realize the farther communication distance, the carrier frequency of the wireless transceiver is set down to50MHz. Meantime, in order to merge the GSM, the W-CDMA, the WLAN, and etc, frequency coverage of the wireless transceiver ranges from50MHz to2.5GHz. This paper aims to design a wideband frequency synthesizer (FS) so as to provide the50MHz to2.5GHz local oscillation frequency for the transceiver.Wideband coverage makes low phase noise and fast locking FS challengable, for instance, quadrature voltage-controlled oscillator (Q-VCO) could not cover50MHz to2.5GHz. In this paper, feasiable structure and circuit techniques are proposed for wideband FS which are done in TSMC0.18μm CMOS technology and verified using both SpectreRF and MATLAB simulators.A dynamic self-bias and auxiliary tail-current automatic amplitude control (AAC) based Q-VCO topology is proposed with frequency coverage from1.54GHz to2.8GHz. While utilize the advantage of the dynamic biasing (reducing phase noise contribution of tail-current flicker noise), the proposed Q-VCO using AAC could be avoided to work in voltage-limited region at higher freuqncies for low phase noise. Simulation results show the maximal amplitude variation within the tuning range is only326mV which is2.25times less than that of Q-VCO without AAC. Moreover, phase noise at100kHz frequency offset and2.8GHz carrier frequency is-100.1dBc/Hz which is2.51dB lower than that of Q-VCO without AAC.A differential dual-slope phase frequency detector (DS-PFD) and dual-branch charge pump (DB-CP) architecture is proposed for fast locking. The differential DS-PFD generates UP1(DN1) and UPo/UPon (DN0/DN0n) used to drive the DB-CP. Timing misalignment between the UP0and the DN0is zero using differential structure. The DB-CP includes a coarse-tuning and a fine-tuning branch. The fine-tuning branch is split into two branches connected by transmission gates, resistors, and a unit-gain amplifier used to reduce dynamic glitches and a source-feedback voltage regulator is designed to increase output resistorof the fine-tuning branch for full-swing. When frequency transition from1.544GHz to1.559GHz occurs, locking time of the FS using the DB-CP is3.9μs which is8.3μs faster than that of the FS using only the fine-tuning branch.A "numerical" technology is proposed used to guide the design of current-mode logic (CML) latch. Moreover, a design methodology is recommended to realize the minimum power CML based2/3divider. Based on the above technologies, a low power2/3divider based programmable multi-mode divider (PMMD) is designed. The divider ratio ranges from75to150, and simulation results show power consumption of the PMMD is1.62mW and phase noise at10kHz and100kHz are-136.41dBc/Hz and-141.57dBc/Hz respectively.By this work, a50MHz to2.5GHz FS chip and the wideband FS based frequency-modulated transceiver could be further realized. Besides, the proposed circuit techniques could guide the design of some other RF-end modules, for instance, the technique used to improve tail-current noise contribution in Q-VCO could be used in Gilbert based mixer. |
PDF Full Text Request