Design Of 0.18μm CMOS High-performance Up-conversion Mixers

In the last few years, the growing demand for RF and wireless applications has attracted a great deal of researches on designing high performance and low cost RF integrated circuits and systems with the advanced CMOS technologies. The RF and wireless communication devices are required to be smaller size, lower cost, lower power and higher performance. Accordingly, the RF building blocks regarding transmitter and receiver circuits are required to be improved. In the RF transceiver front-end, one of the indispensable analog blocks is the up-conversion mixer. The purpose of an up-conversion mixer is to convert the incoming intermediate frequency (IF) signal to a radio frequency component for reliable transmission. In this paper, designed in the 0.18μm CMOS technology, two type of high performance up-conversion mixers have been proposed in the frequency band of 2.4 GHz.Firstly, this paper briefly illustrates the research status of the transmitter architecture and typical up-conversion mixers, and the basic theory about the mixer has been introduced. Secondly, the current-mode techniques and high linearity methods about the CMOS mixer have been analyzed. Thirdly, designed in the 0.18μm CMOS technology, the improved and current-mode up-conversion mixers have been proposed, respectively. Finally, the layout and the post-layout simulation results about two type up-conversion mixers also have been illustrated. The main achievements of this work consist of following aspects:(1) The current various configurations of the transmitter and typical up-conversion mixers are analyzed and summarized systematically, also the basic theory and parameter about the mixer has been illustrated.(2) A 0.18μm CMOS improved Gilbert high-performance up-conversion mixer has been proposed. The proposed mixer uses the dual current-reuse and current-bleeding techniques in both the driver and switching stages with a simple impedance degeneration. The post-layout simulation results show that the mixer core only consumes 4.8mW under a supply voltage of 1.2V, the circuit provides 6.3 dB of conversion gain and the input-referred third-order intercept point (IIP3) of 13.45dBm, the double-sideband noise figure is 11.5dB, while the chip area including testing pads is only 0.7mm×0.8mm. The proposed mixer has shown the excellent post-layout simulation results. (3) A 0.18μm CMOS high-performance current-mode up-conversion mixer has been proposed. the mixer is by using the input current-squaring circuit of cross-coupled class AB topology as the input stage and it shares the output loading with the capacitive cross-coupling techniques which can realize the current mode input and output. The post-layout simulation results show that the mixer only consumes 6.8mW under a low supply voltage of 1.2V, the circuit provides 6.5 dB of conversion gain and the input-referred third-order intercept point (IIP3) of 15.3dBm, while the chip area is only 0.7mm×0.8mm including testing pads. The proposed current-mode mixer has shown the excellent post-layout simulation results.The proposed up-conversion mixers are simulated by version 6.1 of Cadence SpectreRF with Chartered 0.18μm RFCMOS process parameters. The post-layout simulation results show that it has a similar performance compared to the recently published up-conversion mixers.