Research And Design Of Inner Decode On DVB-T

Convolutional code is extensively used in current wireless system of communications.As a maximum-likelihood algorithm of decoding for Convolutional code, Viterbi algorithm has been considered as the best decoding algorithm for its high speed and efficiency. This thesis mainly focuses on the implementation of Viterbi decoder for (2,1,7) Convolutional code which will be used in decoding system of inner code for DVB-T. Viterbi decoder works at the mode of soft-decision carrying a constraint length of 7 and code rate of 1/2.In this thesis, basic knowledge about channel code are firstly explained. Then,in order to dig out the most important error-control code,this article gives the concept of Convolutional code and analyses the theory of Viterbi algorithm. The balance between the performance and computational complexity has been put on large importance. Finally, a Viterbi decoder supporting QPSK modulating for DVB-T has been designed.The major work is as following:1) In this design, soft-decision decoding is used and input symbol is represented as being level 8 quantified. To aim at the easy implement by hardware circuits, the algorithm to compute the Euclidean distance has been simplified.2) The architecture of partly parallel has been used In ACS unit,which meet the speed demand of decoding while saving the chip resources.3) Path metric memory is organized with a new method named "ping-pong" which simplifies control unit and optimize the timing of system.4) Compared to the traditional register exchange method, backtracking algorithm has the merit of reducing the usage of register. To improve stability of system and reduce requirements of clock frequency, a new design that multi-way surviving paths at different times trace simultaneously has been used in Viterbi decoder.5) FPGA design of (2,1,7) Viterbi Decoder has been performed in QuartusⅡ7.2 platform using the VHDL hardware description language. Finally, verify its correctness through observing the result of simulation. This design is reconfigurable and can support other types of convolutional codes, such as (2,1,6), (2,1,9) and so on.