| With the development of the DDR technology, the UI and rating voltage drops that lead to more signal integrity problems. The accuracy of traditional simulation method is not good enough for DDR bus. That cause the simulation result is deviated to real waveform, and weaken the guidance for design by simulation.This paper introduces the signal integrity theory which includes transmission theory, reflection/crosstalk theory and power integrity theory. Based on the theory of signal integrity, this paper describes the mechanism of SSN which is the typical phenomenon in DDR, and the method of timing calculation in DDR. In order to improve the accuracy of DDR simulation, this paper introduces the methods of modeling with Power-aware SI technology for each component in DDR system, such as, transistor, chip, substrate and PCB. Then try to merge those models together to achieve a real system level simulation. With the power-aware SI technology, it generates waveform with high accuracy in time domain and achieves dynamic timing analysis. This method greatly improve the accuracy of simulation, and really helpful to guide the design. |
