Research On Hign-Speed SerDes Signaling And Equalization

SerDes technique can significantly improve the data transmission rate between the connected I/Os. However, the extremely high transmission rate would pose a series of challenges to the system design. In order to optimize the design space and improve the system’s performance, this thesis presents a deep exploration on the signaling and equalization techniques in the high speed serial chip-to-chip communication systems.Up to date, finding the optimal signaling foramt for backplane transceivers working at25Gb/s and beyond remains quite a challenge. To address this pressing problem, we focus on the multi-level signaling techniques, as in the case of four pulse amplitude modulation (PAM4) and duo-binary, and the multi-phase signaling techniques, as in the case of quadrature phase shift keying (QPSK). Through theoretically analysis, we showed that PAM4, Duo-binary, QPSK signalin techniques fit channel better than Not Return to Zero (NRZ), but at the cost of the signal-to-noise performance by9.5dB,6dB, and3dB, respectively. Behavior-level simulation was performed to evaluate and compare these signaling techniques in25Gb/s and56Gb/s data rate, respectively. The experimental results showed that the noise performacne of QPSK and PAM4was strongly dependent on the channle characteristics.Equalization is the core of the high speed serial communication systems. Currently, the main challenges in the equalization design are the coefficient determination and the joint equalization strategy design. To solve these problems, we studied the equalization algorithms in feed forward equalizer (FFE), continuous time linear equalizer (CTLE) and decision feedback equalizer (DFE), based on which, we proposed a new joint equalization strategy maximizing the SNR margin and, at the same time, minimizing the power consumption.To provide a more effective way to examine and evaluate the performance of the aforementioned signaling and equalization techniques, we designed a high speed serial communication simulation platform which assessing the system’s SNR margin and the bathtub curve. Furthermore, we realized Trellis Coded Modulation (TCM) on this platform to exploit the performance of error codec on the high speed serial chip-to-chip communication systems.