The Design And Research Of High-speed PLL Based On The90nm CMOS Process

With the development of the wireless communications and the growing of theapplication areas, the phase locked loop (PLL) frequency synthesizer which is one of themost important modules is increasingly becoming the focus of electronic engineers’research. The applications of phase locked loop cover lots of areas, from the globalpositioning system (GPS) to the clock data recovery circuit (CDR), and then to thewireless transceivers system and so on. The demands of the performance of the phaselocked loop are different in different application fields, whereas the most important is thatthe performance has a direct effect on the quality of the communication system.Therefore, high-speed, low phase noise, low power jitter, low power dissipation, low chiparea and so on PLL system has been attracted more and more attentions by engineers.This paper describes the basic techniques of the PLL, including the principles of thePLL system circuits and the performance of the system and so on. According to the linearsystem theory, the PLL system mathematical modeling is designed and the stability andthe noise transfer function of each module are analyzed. Making best of MATLAB, thenoise of system module is analyzed and verified, which is the strong foundation of thefollowing circuit design. Then by Cadence the non-ideal effects of the system circuit areanalyzed and verified and the overall circuit is design. Most importantly, the layoutdesign of the chip, DRC, LVS and antenna effect are verified.In this paper, the center frequency of25GHz high-speed PLL frequency synthesizerbased on CMOS TSMC90nm is depicted, whose phase noise is-106dBc/Hz@1MHz andwhose frequency coverage is24GHz—26GHz, namely2GHz bandwidth. Finally, thearea of the high speed PLL system is optimized and the system test PCB is designed toverify the performance of the PLL system. This paper gives the test results of the chipwhich meet the demand of the design.