Researchand Design Of Fully Integrated PLL Synthesizer In Wireless Receiver

With its rapid development, wireless communication technology is widely usedin many applications such as aerospace, digital TV, mobile communication and etc.Frequency synthesizer (FS) is the key block and becomes the bottleneck for theperformance improvement in these systems. And phase lock loop (PLL) is the mostpopular implementation method. Low phase noise and spur, fast locking, low powerconsumption and high integration are all the development direction of PLLFS.A fully integrated PLLFS with low phase noise is realized in this thesis in GPSreceiver project. On principle of up-to-down, firstly, researches on theory of PLLFSand the loop analysis method is presented, and also the non-ideal factors in circuit isdiscussed. Secondly, the loop parameter is decided according to the systemspecification；the behavior model is established by using MATLAB tool. After systemlevel simulation，detail circuit design is completed with solution for non-ideal factors.Finally, the layout design of whole PLLFS and post simulation are finished.Based on fully integrated, low phase noise design emphasis, main researchcontents includes: First, the linear model and transfer function are deduced carefully,based on which the method to analysis the loop stability and noise contribution ispresent. Moreover, provide the system level optimization of noise. Second, theresponding solution is proposed after discussing the non-ideal factors of the key blockphase frequency detector (PFD) and charge pump (CP), and then the circuit design iscompleted. Third, capacitor multiple technique is employed when implementing theloop filter to reduce the area, which make sure the fully integration of PLLFS. Fourth,the switch capacitor array technique is adopted to reduce parameter Kvco whendesigning the LC-VCO, which improves the phase noise performance.The project is designed with TSMC0.18μm1P5M RF process. The postsimulation results show that the output signal frequency is1571.328MHz which isorthometric. Phase noise achieves-94dBc/Hz@10KHz,-99.2dBc/Hz@100K,-123.7dBc/Hz@1MHz respectively. The lock time is less than20μS. The total currentis about13mA with1.8V power supply. Meanwhile the PLLFS is fully integratedwhich meets the system requirement of this GPS receiver.The achievement of this work provides lots of useful comments and a certainreference value on the design of low phase noise PLL frequency synthesizer circuit.