Design And Implementation Of Low Phase Noise PLL Frequency Synthesizer

Frequency synthesizer is used as frequency source of modern electroniccommunications and electronic computer systems. It’s an essential device and is called asheart of modern electronic system. With the development and widespread use of moderncommunications technology and computer technology, spectrum resources is requiredused to be more intensive, effective and convenient. So increasing demands is asked forthe frequency synthesizer. Frequency synthesizer has been a research focus at home andabroad, more and more high-performance frequency synthesizer is being developed.At first, this paper researched the frequency synthesizer research background,technical indicators, and PLL development at home and abroad. Secondly the theoreticalfoundation of PLL and digital PLL frequency synthesizer is fully introduced. At last twofrequency synthesizers are designed and implemented. The frequency range of the firstone is2.65~3.25GHz, frequency step is5MHz. On the base of full research on all kinds oflow phase noise mixed PLL frequency synthesizer, dual PLL frequency synthesizer isselected to be design program. The output frequency of sub PLL and main PLL are mixedthrough mixer. Then the divider ratio of main PLL is declined, so the phase noise ofsynthesizer is declined. The output frequency of the second frequency synthesizer is1.51GHz. Single PLL is selected to achieve the design goal on the base of selectingappropriate device. After the completion of the two local oscillator design and production,the two frequency synthesizers are tested.After the completion of the two local frequency synthesizer, the two frequencysynthesizers are measured. Test results show that spurious suppression, hopping time andoutput power meet the design requirements and achieve the low phase noise of frequencysynthesizer. It is proved that through selecting appropriate device and design program toachieve low phase noise synthesizer is feasible.