Finfets Devices And The Optimization Of Geometric Parameters

As a result of CMOS scaling to follow the pace of Moore’s Law, increased subthreshold leakage become the main factor hindering the process of further development when shrinking feature size. To reduce the leakage current and improve the stability of the device has become an important challenge to a sub-20-nm gate length. The FinFET is a promising transistor structure because of the absolute advantage in terms of suppressing the short channel effect. This article describes the characteristics of the FinFET, produce process, development, strengths and challenges. Then the author simulate SOI FinFET using Silvaco TCAD and optimize the geometric parameters to improve device performance. The main research results are as follows:After simulating output characteristic curve and transfer characteristic curve, we draw the conclusion:Firstly, when Fin width increase, the thickness of the oxide layer or the doping concentration in channel decrease, the current driving capability can be improved. While, the Fin height or the oxide layer thickness or the channel doping concentration increasing will significantly reduce the current drive capability. Furthermore, FinFET with wider Fin are more easily influenced by gate voltage.This paper also studied device characterization parameters of FinFET and found that Fin height increasing will reduce the subthreshold swing, DIBL and improve device switching speed, reduce the leakage current. By contrast, with increasing width of Fin, the subthreshold swing and DIBL value increases, device performance deteriorate, short channel control ability becomes weaker. When the value of Fin_H/Fin_W is about2.25, SOI FinFET will benefit most.Finally, after simulating oxide layer and finfet with capping layer, we found when the oxide layer thickness increased, subthreshold swing and DIBL value increases, and the control ability of gate becomes weaker. Oxide layer thickness decreases will bring the improvement of the device speed and the leakage current reduction. On the other hand, the hydrostatic stress from capping layer will enhance performance of FinFET.