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Design Of RF Front-end Key Circuits Applied In Carrier Aggregation

Posted on:2014-11-13Degree:MasterType:Thesis
Country:ChinaCandidate:L HeFull Text:PDF
GTID:2298330434966304Subject:Integrated circuit engineering
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With the ongoing high demand on wireless communication, the4th generation wireless technology develops popular. LTE Advanced supports maximum baseband bandwidth up to100-MHz. Practically such wide bandwidth does not exist in low frequency band, while it needs huge investment for base station construction to operate in high frequency band. Industry proposes carrier aggregation to fulfill specification of LTE Advanced, to cut down upgrade cost and to enhance efficiency of spectrum resource, which combines discrete narrow spectrum resource to wide carrier band. As it makes full use of spectrum resource and enables software upgrade rather than hardware upgrade for base station to support LTE Advanced, it wins wide support from wireless operators. For user equipment, besides software upgrade, new hardware design is needed to support carrier aggregation, which includes multi-channel transceiver and the corresponding require on specification. We focus on the key circuits of RF front-end applied in carrier aggregation, investigate application and technology background, propose circuits design and verify through simulation.Principle of carrier aggregation is firstly introduced, and then the impact on transceiver specification is discussed, after that we study the detail of principle and design method of mixer. Carrier aggregation receiver increases demand of performance on mixer, especially linearity of mixer. We propose a mixer to fulfill that, driven by25%-duty-cycle LO signal. Its conversion gain, linearity and noise performance is increased by greatly reduce overlap time of LO signal. At last a mixer circuit operating at1.9-2.6GHz is design, simulation result show that it perform well in some extent. Some analysis is made to improve mixer’s performance.
Keywords/Search Tags:carrier aggregation, receiver, mixer, CMOS, 25%-duty-cycle
PDF Full Text Request
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