Research On Large-capacity And High-speed Storage Device Based On DDR

In the era of information explosion, how to realize high-speed and large-capacity data storage is becoming an urgent problem to be solved. Based on the study of DDR memory and drawing lessons from SATA alternativing ATA method in which parallel communication was improved for serial communication, this research presents the design scheme of SDDR memory. And based on SDDR memory, system further extends to SDDR storage arrays. It uses file system on data management of storage arrays. Both the data transmission speed and access rate of the system are improved, while the capacity gets expanded at the same time.According to the designed program, this research has realized the hardware circuit design and completed the debugging and verification of code.Specific work is as follows:1. Define frame format of data transmitted in the SDDR storage system. Describe the design scheme of SDDR memory. Use VHDL language to describe the functional module design which includes host interface, the host and memory uniform node interface, write only bus and converting unit. Complete the program debugging simulation and analyze the performance of the system.2. Introduce the process of building SDDR memory array. Based on SDDR memory, by improving the host interface and splitting and integrating host data to improve the function of the SDDR memory array, Complete using VHDL language to describe the module design, debugging and simulation of the system. At last, analyze the performance of the system.3.Design, weld and debug the hardware circuit. The system has a board-level verification. According to the functions of the system, it is concluded that the whole design scheme of hardware platform, and introduces selecting appropriate chip method, then according to the FPGA chip peripheral interface characteristic, system designs circuit principle diagram of DDR memory module, power supply module, Ethernet module and serial module. Layout for PCB which using12layers structure. Also introduce the note on the problems arising during the welding and debugging process and the corresponding modification methods in detail.After the hardware circuit debugging completed, verify the correctness of the SDDR memory array design.4. File system accesses SDDR storage array design.Achieve the memory management of SDDR arrays, describe the structure of file system of the storage array and introduce the design about file formatting, storaging and reading.SDDR memory array is a new type of storage system, using the unified node interface and write only bus to set up the architecture, and build a reasonable file system on the FPGA to manage data. The system by increasing the transmission speed of BoW and mounting a plurality of memory to the BoW and forming an array to achieve improving the data access speed and expanding storage capacity.At present, the SDDR memory array has been verified on designed circuit board. System serial clock reaches450MHz and memory space for the8DDR memories is256MB. System with strong anti-interference performance and transmission reliability is an innovation in the memory areas.