A Study Of Low Power Methodology Of Standard Cell Based On EDA Tools

Along with the development of technology, advanced techniques for integratedcircuits processing continually reduce the size of integrated circuits and increase itsintegration. But, wasted power percentage in total power dissipation continuallyincreases with techniques scaling. When the design steps into nanoscale world, more than50%or even higher percentage of total power dissipation is due to leakage power in wasted power.Therefore, low-leakage power design is an effective technique for controlling this problem inintegrated circuits design.The methodology of standard cell based on EDA tools is most commonly used in the design ofdigital integrated circuit and plays a significant role in digital chips design. The chips design andapplication of Low-leakage power depends on the design of standard cells of the low-leakagepower. Hence, how to decrease the standard cells leakage power is a valuable design.In the beginning, this paper will utilize low-leakage power of standard cell based on EDA designand generalize it into other standard cells.Then, it summarizes the design flow of low-leakage power standard cell, designs the low-leakagepower performance of the standard cell based on the SMIC130nm CMOS (SMIC13) processmakes it compatible to the cell in the original cell library and provides a technical support for low-leakage-power IC designs.In accordance with technical procedure of standard cell design, this paper will discuss as thefollowing five steps.Firstly, according to the mechanism of production of leakage power, analyzing the leakage powerof standard cell in SMIC13cell library and optimizing the circuit configuration and scale is todecrease leakage power. Secondly, the layout of the low-leakage power cells is in the light of the modified design idea.More importantly, the design process, including height, width, the display of the PIN and otheraspects of standard cells, is strictly operated in accordance with the rule from the techniques rule ofSMIC13.Thirdly, it will complete the P&R library design. It applys ABSTRACT to finish all of thestandard cell’s physical abstract extraction is for the automatic placement and routing in the digitalIC designs.Fourthly, this step will implement on the extraction of Synthesis Library. It achieves the cellcharacterization by utilizing EDA (NCX and HSPICE). Then, it can generate Synthesis Librarywhich can be used for logic synthesis.Finally, an experimental design based on strictly implementation of design rule confirms that theeffect of decreasing the leakage power dissipation in our modified standard cells.