Error-detection And Error-correction Technologies For Processors: Delay Fault Modeling, Design Decisions And Planning

Along with technology aggressively scaling, the design of processors facesproblems such as process variation, noise tolerance decreasing. As these problems arebecoming more and more significant, the probability of delay faults in the circuitincreases. In conventional processor design, clock period is expanded to avoid errorscaused by delay faults, which decreases the speed of the processor. In65nm technologyand below, the lost of speed as a result of avoiding delay faults by increasing clockperiod is too high to meet the requirements. Thus, processors with error-detection anderror-correction have become the focus of research at the present. In view of applicationrequirements and aiming at improving throughput of the processor, a new method ofdesigning processors with error-detection and error-correction has been researched andexplored in this dissertation. The main results of this dissertation are presented asfollows:The representative path based error-detection (RPED) and pipeline stallingbased error-correction (PSEC) are proposed in this dissertation. Thecorrectness and practicability of RPED has been proved and the design rulesare introduced. Experiments on ISCAS'89and ITC'99benchmarks show thatRPED detects the errors with accuracy of more than99.9%. The hardware costof RPED is less than1%. The calculation and simulation results show thatPSEC can reduce average error recovery time by more than30%comparedwith other existing error-correction mechanisms.The probabilistic delay fault model is proposed to estimate the error rate undergiven clock periods when the processor works in power supply voltage andtemperature changing environment. It has been verified by the experiments thatusing probabilistic delay fault model, the clock period of the processor isdetermined on the premise that the error rate is controlled at a certain levelonce the range of power supply voltage and temperature is given.The criterion which gives the sufficient and necessary condition of increasingthe throughput by error-detection and error-correction is presented in thisdissertation. The mathematical expression is universal and can be into general application. It is pointed out that the validity of increasing the throughput byerror-detection and error-correction relies on the probability density function ofthe circuit delay and the average error recovery time, and has nothing to dowith the implementation of error-detection and error-correction.Based on the research above, a design method and flow of processors witherror-detection and error-correction has been explored. The circuit of theprocessor with error-detection and error-correction is acquired from theoriginal pipeline processor circuit. Implementation of OpenRisc1200processorshows that the design method in this dissertation can improve the throughputby10%. Compared with other existing methods, the cost of error-detection anderror-correction is reduced by53%and average error recovery time is reducedby more than45%.