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.10 200msps Pipeline Dac Research And Design

Posted on:2009-08-03Degree:MasterType:Thesis
Country:ChinaCandidate:J LiFull Text:PDF
GTID:2208360245961114Subject:Microelectronics and Solid State Electronics
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Digital-Analog Converter (DAC) is widely used in digital-analog mixed signal processing system, for instance, image signal processing system, wired and wireless telecommunication systems, and etc. The rapid improvement of digital technology demands high performance DAC. Higher speed, higher resolution, lower power dissipation and supply voltage are the direction of development.A general introduction on Digital-Analog Converter study of domestic and aboard is presented. The principle and structures of DAC, and typical converters are analyzed. Advantage and disadvantage of different converters are described. The pipeline DAC is determined according to the specifications demanded.Based on switched capacitor technology, pipeline DAC uses Multi-phase non-overlapping clocks to control the capacitor charges to redistribute and get the weighed sum of the charges of different bits and then gives out the final buffered output voltage to the MSB. Sampling capacitor arrays, input timing adjustment, output buffer, and multi phase clock generator are consisted in the pipeline DAC.Three exploratory discussions and analysis of research and development are performed after analyzing the non-ideal elements that affect output accuracy and speed. Normal open and normal closed dummy MOS arrays are added to increase the linearity, and parasitic capacitors are minimized. The holding phase is added to the output buffer to increase the spurious-free dynamic range (SFDR) of the high frequency inputs and not return to zero (NRZ) DAC is achieved. Delayed Phase-Locked Loop (DLL) is used to generate the multi phase clock that can share with other blocks. Then 10 bit 200MS/s pipeline DAC is implemented after comprehensive analysis.When simulating using TSMC 0.25μm CMOS process, the results show that it achieves DNL less than 0.25LSB, INL less than 0.8LSB, SFDR steady larger than 70dB in frequency range between 0 and Nyquist frequency, which is much better than current steering DAC of the same specifications. The power dissipation of the whole DAC is 40 to 50mW, which is significantly less than current steering DAC of the same specifications. The advantage of linearity and power dissipation make it possible for pipeline DAC to become an economic substitute of current steering DAC.
Keywords/Search Tags:Digital-analog conversion, DAC, Pipeline, Integral nonlinearity, INL, Differential nonlinearity, DNL, Spurious-free dynamic range, SFDR
PDF Full Text Request
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