Design Of CMOS Low Noise Amplifier With High Linearity

Nowadays, more and more people prefer to use wireless communication in their dailylife. As a consequence, it is a golden period for the development of wireless communication.The performance of RF front-end plays a critical role in a good wireless system. It is supposedto have low power consumption, high level of integration, low bit error rate and goodperformance. The biggest advantage of CMOS process is its low cost and it is convenient tointegrate both RF circuits and digital circuits in one piece of IC chip. Hence, the design ofRF integrated circuits based on CMOS is increasingly popular.Low noise amplifier (LNA) is always located in the first stage of a wireless receiver. Asa result, the noise figure, the reflection coefficient, the power gain and the linearity of anLNA are of great importance which may influence the wireless receiver greatly.This paper analyzed each performance parameter of the high linearity LNA, whichinforms the designer how different factors influence its performance. After comparing severalcircuit architecture as well as different ways to improve the linearity, the author chose anoptimal method to accomplish circuit design. Based on TSMC CMOS process, thesimulations of circuit performance lead to a set of design methodology. In the end of thepaper, the test result of the high linearity LNA is presented which is in accordance with thesimulation results.The power supply of this chip is3.3V, which consumes45mA current. The IC test resultsshow that, at working frequency, its noise figure is less than1.7dB, power gain is14.9dB,input reflection coefficient is-12.1dB, output reflection coefficient is-21dB and IP3referredto output power is29.1dBm. The LNA chip works normally, and it can satisfy with the designrequirements.