Design Of L-Band CMOS Low-Noise Amplifier

The Global Navigation Satellite System has gradually become an indispensable part of spatial information acquisition.Its application range has expanded from the professional market to the civilian market.The importance of the navigation receiver front end as a major component of the satellite navigation system is self-evident.The low-noise amplifier is the first module used in the front-end of the navigation receiver.The performance of the low-noise amplifier will undoubtedly directly affect the use conditions and application range of the navigation receiver.Based on the application characteristics of the navigation receiver,in addition to satisfying the requirements of the system,low-noise amplifiers must also ensure high enough linearity to suppress signal interference.This article is exactly the research design of low-noise amplifier based on L-band in CMOS process.After introducing the research background and the existing research results,this paper analyzes that the existing optimization structures are only suitable for the optimization of a single index.In practice,it is also necessary to trade off the requirements of each index.This article first analyzes the indicators in detail,and briefly analyzes the system's specifications through the topology of low-noise amplifiers.After a trade-off between the requirements of the specification and the structural characteristics,the source-degenerate cascode amplifier used in this design was analyzed in terms of specific indicators and structures.And use the additional optimisation in the linear design.Compared with several existing optimization schemes,the derivative scheme suitable for this design was selected and a specific analysis and design was made.Based on the SMIC 180 nm process,the circuit was designed.Through the analysis of the overall circuit performance,the single-stage low-noise amplifier is further proposed for performance requirements at all levels.After optimizing the design of the low-noise amplifier of each stage,the design of the circuit diagram is completed.In the layout design,due to the special characteristics of the high-frequency circuit,the active and passive components of the circuit are further designed.Finally,the circuit design is further optimized through post-imitation results.Finally the chip designed in this paper were fabricated.At the end of this paper,the chip is bonded on the pcb board,and the chip is tested.Firstly,the test conditions and the instrument used for the test are introduced,and then the chip is tested and the test result is obtained.The chip uses 1.8V and 3.3V together to supply power.At the operating frequency,the noise figure of the low noise amplifier is 4.3db,the gain is 18 db,the S11 is-16 db,and the S22 is-21 db.The output third-order intermodulation is 19.7db.The test results are in accordance with the results of analysis and simulation.Demonstrate the effectiveness of circuit design,layout design,and optimization results.The chip was working properly,and the performance indicators met the design requirements.This project was finally completed.