Research On Firmware Optimization Algorithm In Solid State Drive

Compared with traditional hard disk drive,solid state drive(SSD)has the advantages of low power consumption,fast read and write,shock resistance,noise-free,and light weight,which makes it replace traditional hard disk drive in many fields.However,due to the inherent physical characteristics of the flash memory,the SSD retains many disadvantages such as asymmetric read-write performance,erase before write,and limited program/erase cycles.In addition,different flash have different storage densities,read-write performance and cost,and the SSD composed of one single flash media can't meet the increasingly diverse requirements in terms of performance and cost.Focusing on the above problems,this paper studies the optimization method of the SSD's buffer management layer and hybrid SSD's flash translation layer,to achieve the goal of improving the overall performance of SSD and prolonging the service life of SSD.The main contributions of this paper include the following two points:Aiming at the poor adaptation of existing buffer management algorithms to different workloads and flash translation layers,this paper proposes an Advanced Adaptive Least Recently Used buffer management algorithm(AALRU)based on the cross-layer design idea.AALRU adaptively adjust the structure and parameters of the buffer according to the upper workloads and the underlying flash translation layer state.Specifically,AALRU can dynamically adjust the ratio of read buffer and write buffer according to the read-write characteristics of the upper workloads and then improve the buffer hit rate.For dirty page clustered write-back,AALRU can dynamically selects the appropriate clustered write-back by sensing the underlying flash translation layer state through the writing amplification factor.Then AALRU enhances the continuity of the write request and reduces the garbage collection overhead of the underlying flash translation layer.Experimental results show that AALRU has the best adaptability under different flash translation layers and different test workloads and it can achieve the optimal or near-optimal results.Specifically,compared with BPLRU,FAB,CFLRU and ADLRU,AALRU improves the buffer hit rate by 96.9%,144.2%,3.0% and 30.9%,reduces the number of block erase by 21.3%,27.5%,17.7% and 23.5%,and reduces the average request response time by 12.4%,24.7%,14.1% and 21.6%,respectively.For the flash translation layer design of hybrid SSD,this paper proposes an hybrid on-demand flash translation layer algorithm,referred to as HDFTL.HDFTL considers both the design of the mapping buffer and the allocation of data in different flash media and adjusts the design parameters of mapping buffer in the flash translation layer according to the wear degree of different flash partitions.Specifically,first,HDFTL divides the SLC(Single-Level Cell)flash area into a data block area and a translation block area,and uses the MLC(Multi-Level Cell)flash area as a data block area.The translation block area is aligned by 2KB pages,and the data block area is aligned by 4KB pages.The complete mapping table is stored in the translation block area,and the partial mapping items are loaded into the cache as needed,which greatly saves the cache overhead of the mapping table.Second,HDFTL uses the consistency of mapping updating and data updating and the cache mapping table information to recognize hot data.Then HDFTL can realize the reasonable allocation and migration of hot and cold data in SLC and MLC.Finally,according to the relative wear degree of SLC and MLC,HDFTL adaptively adjusts the hot data identification benchmark by adjusting the hot zone rate of the cache mapping table to achieve relative wear leveling of SLC and MLC.Experimental results show that compared with CFTL and Comb FTL,on average,HDFTL reduces the average request response time by 34.4%and 18.2%,and reduces the equivalent total block erase counts by 45.1%and 18.5%,respectively.At the same time,the wear degree of SLC and MLC is more consistent,and the memory overhead of the cache mapping is reduced by 96%.