Resrarch And Implementation Of Axie Interface Technology

With the development of modern science and technology, automatic test systemget more and more attention by the governments. As a new generation of automatictest system architecture, AXIe architecture specification was authored by the AXIeConsortium companies. AXIe architecture based on AdvancedTCA and referenceexisting LXI and PXI bus technology. The AXIe backplane supports two interfacestandards, LAN and PCI Express, the LXI and PXI Express bus technology wasfusioned among AXIe architecture effectively.Based on the analyzing of AXIe architecture specification mainly from themechanical properties, intelligent platform management system, data transfer andsoftware standard. Based on the plan,this thesis submit the AXIe interfacetechnology proposal through the PCI Express communication mode,and the Arria IIGX-family with embeded PCI Express hard IP core is chosen as the chip toaccomplish the interface communication. Based on the AXIe architecturespecification request, the zone1and zone2hardware design was accomplished,suchas power supply, intelligent platform management bus, local bus, trigger bus, timinginterface and fabric interface singal.In order to meet the interface design of generality and reusability, the Qsysdesign flow is introduced into FPGA logic design. The AXIe interfacesubsystem,DDR2memory logic and function-specific logic was designed accordingto the actual demand,and two kinds of DDR2memory logic was designed to meetthe application of a large amount of data transmission according to the differentapplication situation. The PC applications was designed by LabWindows CVI,andthe instrument drive was accomplished by using VISA.In order to verify the feasibility of interface proposal,a128relays module wasdesigned based on the AXIe interface technology proposal,and the test system ofAXIe was built to for the functional and performance analysis of the AXIe interface.Based on the testing result,the module can accomplish PCI Express communicationand work properly in the x1, x2and x4mode. The DDR2memory circuit canaccomplish data storage capabilities. The implementation of module control can beachieved by using AXIe backplane’s star trigger and trigger bus.