The Design Of High-speed Data Acquisition And Transmission Interface Of AXIe

The new generation of automatic test bus standard AXIe(advanced TCA extensions for instrumentation)has the advantages of large design space,high transmission rate,strong compatibility,high power and strong heat dissipation,which can meet the development needs of large high-performance modular instruments.High-speed data acquisition technology plays an important role in test systems and is widely used in radar communications,electronic measurement and other fields.In this paper,AXIe bus architecture and high-speed data acquisition technology are combined.Based on the highspeed data acquisition and transmission interface technology based on AXIe bus,the highspeed data acquisition design based on AXIe bus is completed.Firstly,the key technology of time-interleaved sampling method is studied.Twochannel ADC is used to develop dual-channel time-interleaved sampling module,and signal conditioning circuit is designed to improve the anti-interference ability of the sampling system.For the phase adaptation problem caused by time-interleaved data sampling,this paper selects the dedicated clock chip to design the clock system to generate low-jitter and phase-adjustable clock signals,which improves the accuracy of the two-channel ADC sampling clock.Secondly,in order to facilitate the system to restore and store the sampling waveform,this paper uses FPGA to process two sampling data,including cross-clock domain processing,adding header,clock synchronization and data splicing.Aiming at the problem of rate mismatch between data acquisition module and data transmission module,a large-capacity data buffer module is designed to prevent the loss and mis-transmission of sampled data.For the FPGA comes with DDR3 IP core interface is complex,and read and write trouble,read command and write command share a set of control bus.In this paper,the read/write control module is added on the basis of the original IP core to simplify the read and write timing.The FIFO module is added to enhance the continuous read and write capability of the cache module,and the read/write arbitration module is introduced to time-multiplex the control bus to avoid read and write conflicts.Finally,through AXIe's PCI Express interface as a transmission channel,PCIe 2.0 fourchannel mode is used to increase the transmission bandwidth.For the communication between the FPGA and the PC through the PCIe interface,the protocol realizes the problem of complex and low actual bandwidth utilization.This paper adopts RIFFA(the architecture of communication between PC and FPGA through PCIe)to realize the design of the data transmission module.The PCIe bus protocol consists of The FPGA directly calls the IP core implementation.In this paper,the Xilinx KC705 development platform and two ADC sampling boards are used to form a verification platform,and the FPGA integrated development tool Embedded Logic Analyzer(ILA)is used as a verification tool.The standard sinusoidal signal is used as the measured signal to complete the verification of the data acquisition module,the data buffer module and the data transmission module,and the overall system.The results show that the interface module can realize the time interleaving sampling function,complete the high number buffering and transmission of data,and can be used for the development of AXIe instrument module,which has certain practical value in the field of automatic testing.