Architecture Research Of ASIP Base On Petri Net

ASIP(Application Specific Instruction Set Processor) is the processor forcustomizable application-specific areas , it can be Dedicated design for specificapplicationsit ,can well solve some of the problems encountered in the design ofembedded systems, it has been more widely used in the embedded field.Then design processor technology of RISC , it’s rising in the eighties of the lastcentury,In Currently,RISC and CISC is the two of Mainstream technology , becausethe instruction set of RISC technology is simple, easy to decode, it more applicationsin design.The pipeline design is a very important part, the use of the pipeline cangreatly improve the speed of instruction execution, MIPS is a typical version of RISC,pipeline technology is well application On the MIPS architecture. In this paper adetailed description of the MIPS architecture , through the research of MIPSprocessor,design register reactor,arithmetic logic unit (ALU), decoder and so on in theQuartus software ,and design instruction fetch (IF), decode (ID), execution (EXE),access to the register (MEM), the register write-back (WB) ,the five pipelinemodulethe for MIPS processor, processor synthesis and simulation results show thatthe design of this processor is correct.Petri net’s concurrency features make it has a great superiority in the pipelinemodeling. The Petri net model can be used HDL (Hardware Description Language) todescribe ,Compiled and integrated simulation of Petri net models in the existingsoftware platform ,and make Petri net library in the Quartus. Modeling on the basis offive pipelined MIPS processor based on the previous design,it Prove Petri netdescription of the ASIP pipeline is feasible.