Pipeline Research Of ASIP Base On Petri Net

ASIP(Application Specific Instruction Set Processor) is a new kind of the chip with proc-cessor structure,it can be Dedicated design for specific application, to optimize the embeddedsystem Through the custom function. improve the efficiency of the implementation of embe-dded devices, with the development of the embedded field, ASIP has been widely applied inthe embedded field.With the expansion of ASIP application,the design cycle, design cost and othernonfunctional requirements of ASIP are becoming more and more important.And the designof pipeline structure is one of the most complicated part in ASIP design, traditional ASIPpipeline design method has been couldn’t meet the requirements. Based on traditional designcycle is long, changing the structure of the underlying logic is very difficult, discusses adesign methodology of ASIP based on "description-synthesis", pipeline structure model isbuilt based on Petri Nets. the PNML(Petri Net Markup Language) description mapping theHDL description of RTL by corresponding mechanism, which accelerates the speed ofprocessor design.Paper follows the design methodology of "description-synthesis", using Petri nets toASIP pipeline structure modeling, presents three different Petri Nets based on differentarchitectures, uses PNML to describe pipeline based on Petri Nets.General Petri Nets ofpipeline and its Dynamic simulation are accomplished by ASIP design IDE. Translates thedescription of PNML into HDL description of RTL by the IDE of ASIP design which cansynthesize Petri Nets, uses Altera Quartus II to test and verify, finally downloads it into theFPGA(CycloneⅢ Chip) to watch results of the experiment.