Key Problem Study On Configurable And Extensible Processor

With the rapid development of the integrated circuit design technology as well as the increase of the market requirements, SoC is playing more and more important roles in the field of the embedded system. But with the approaching the deep submicron era, the ASIC-centric SoC design methodology cannot satisfy the users'requirements changing fastly because of the too long period of design, which will be solved by the configurable and extensible processor-centric SoC design methodology. This paper will discuss in details about several key problems needing to be solved urgently in the configurable and extensible processor design.Firstly, this paper presents a fully configurable and extensible processor template based on Transport Triggered Architecture, named as T*CORE which will be the underlying platform for the following research. Then an automatic hardware/software co-design methodology is proposed according to the features. The designers can complete the architecture customization, high-level modeling, the automatic generation of software toolset and the hardware netlist through the design flow.Secondly, as the highly efficient compiler is one of the key aspects affecting the performance of the T*CORE processor, this paper introduces a retargetable compiler trajectory based on intermediate format. For the task of register allocation in this trajectory the linear scanning algorithm is adopted in this paper to resolve the existing problems in the traditional algorithm, for example, the over high time complexity, space complexity, and the over hyperbaric variable pressure to the physical registers. For the instruction scheduling this paper firstly proposes a hybrid operation scheduling algorithm based on critical path and list scheduling, but the scheduling performance is limited because of the local optimality in the algorithm. Then the problem of instruction scheduling is solved by the genetic algorithm with the proposed minimal latency matrix and integer linear programming model to processing every kind of constrains and conflicts, which results in a better instruction level parallelism.Thirdly, system level modeling is very import to the architectural design space exploration of SoC, but the highly flexibility of T*CORE increases the complexity and difficulty of system level modeling. For this problem this paper proposes a system modeling method based on object-oriented technology with SystemC simulation technology. A cycle accuracy and bit accuracy electronic system level model is designed based on this method, which makes the modeling have many advantages such as high flexibility, easy extension, loose coupling fast speed of simulation and high accuracy.Fourthly, too long width of the instruction and the rapid expansion of code size are two drawbacks in the T*CORE because of the architecture features. For the former the method of reusing NOP operation is presented in this paper to store the long immediate data so as to shorten the width of instruction. For the latter the arithmetic coding is introduced to compress the code size in which the Morkov model is used to get the transition probability resulting in higher compression ratio.Finally, a processor chip named T*CORE A0424v1 for MP3 decoding application is presented in this paper, which is fabriced in GSMC 0.13μm CMOS MPW process technology. Its highest clock frequency is 150MHZ, the area of chip is about 3.25mm2 and the static power is 2.27mw. Then this paper uses it as a co-processor coordinating with a general purpose processor C*CORE to construct a multi-processor SoC for audio applications. Only needing the clock frequency of 33MHZ, this SoC can complete the high-quality MP3 real-time decoding, whose SNR is over 85db and dynamic power is only 9.23mw. Thereby it proves that using configurable and extensible T*CORE processor as the basic unit of SoC will result in the very high performance/cost ratio and design flexibility.