Design Of Instruction Set Simulator And Integrated Development Environment Of Configurable Processor Based On Tta

With the rapid development of the integrated circuit technology, SoC is playing more and more important roles in the field of the embedded system. The ASIC-centric SoC design methodology cannot satisfy the users'fast-changing requirements because of the long design period. To meet the requirements of performance, size, time-to-market, power comsumption in embedded processor, the configurable and extensible processor based on Transport Triggered Architecture (TTA) appeared that can achieve the architecture customization quickly and effectively according to actual demand.This thesis designs a hardware/software co-design integrated development environment for the configurable and extensible processor, T*CORE. Through the environment, the designers can complete the architecture customization quickly, and then generate the instruction set simulator using the architecture description file and operation description file. The entire development environment is a toolset with design, simulation, evaluation and optimization, which includes features as processor architecture customization, coding of register and high-level simulation modeling and so on, which is a process that help designers to find an optimal architecture for the given processor architectures.Design space exploration is conducted to find a desirable architecture quickly and effectively. Under this exploration, there is a need to generate specific simulators for all the candidate architectures. The highly flexibility of T*CORE architecture increases the complexity and difficulty of the model of the instruction set simulator. For this problem, a fast generation methology based on architecture description for retargetable simulators is proposed in this thesis. The method combining the object-oriented technology and SystemC simulation technology issued, and a cycle accuracy and bit accuracy instruction set simulator is achieved. Finaly, the experiments has been done to verify the correctness and performance of this fast generation toolset and the design methology.