| As people become increasingly demanding aspects of the processor, thetraditional superscalar processor due to the obstruction of unsustainabledevelopment, sub-chip processor architecture came into being, with blocks ofatomic, explicit communication features such as EDGE (Explicit Data GraphExecution) instruction set architecture for adaptation of the processor chip hasbeen widely applied, using EDGE instruction set architecture, withconfigurable features of the target processor is known as EDGE processor canbe configured, which can be EDGE processor configuration feature is theprocess or thread according to the different number of different physical corelogic check their processed form, it can be configured EDGE processor has ahigher flexibility, adaptability, and thus become the domestic and internationalresearch hot; due execution unit is a pivotal part of the processor, this paperfocuses configurable EDGE processor execution units carried out a detailedstudy and design.Classic scalar, superscalar processor execution unit typically contains onlysimple arithmetic logic unit, the reservation station and other structures;EDGE processor execution units in addition to containing an arithmetic logicunit, the support block also includes the characteristics of atomic instructioncache, the status buffer, the operand buffering structure, and display thecommunication features to support the corresponding feature of the structure;configurable EDGE processor execution units in addition to containing aspecific function can be configured to support a configurable mechanism, itsinstruction buffer state buffer, the operand buffer, the arithmetic logic unit andother structures in number to the processor’s execution units and EDGE aredifferent.Configurable EDGE processor execution units can be configured to adjustthe execution of the current program mechanisms most reasonable physicalauditors, the instruction buffer state buffer operand buffer contains128buffertank, just to accommodate a corresponding instruction block decodedinformation, inst_select (instruction selection) Select the command structure of the block can be executed with the highest priority one instruction, thisinstruction is called definite instructions, inst_read (instruction fetch)structure from a definite command, two bypass (bypass) Directive can beexecuted in the selected highest priority instruction, arithmetic logic unitcalculates the final result of the selected instruction.EDGE on the design of the processor execution units can be configured tothe specific structure of verilog achieve, modelsim simulation and designcompiler integrated functions, the results show that the designed EDGEprocessor can be configured to perform a single specific structure and functionproperly, it is possible for the current resource adjust the utilization of thephysical execution of auditing, capable of executing a block of instructions inan instruction of the highest priority, can be implemented in hardware, usingsmic18technology library, can work at a frequency of235Mhz. |
