A Research Of Buffered LDPC Decoder In SC-FDE System

In the new generation of wireless telecommunication system, it has a higherrequirement on the data transfer rate and its reliability. How to achieve such ahigh-speed and reliable transmission on the limited spectrum resources has become atop topic in the present research. The low density parity check (LDPC) based on singlecarrier frequency domain equalization (SC-FDE) system is quite a good solution to sucha problem. Based on the system, the paper not noly discusses some basic technologies,but also presents a buffered LDPC iterative decoder to the system. The main contentsare:(1) Different kinds of decoding algorithms to the LDPC code are first discussed,including belief-propagation(BP) based decoding algorithms and bit-flipping (BF)decoding algorithms based on hard decision. A progressive edge growth(PEG) basedquasi-cyclic(QC) LDPC code is adopted to realize the decoding algorithms above. Theperformance of the above algorithms are discussed and compared.(2) A buffered iterative LDPC decoder is introduced to improve the throughput ofthe system. To achieve the nearest performance of the non-buffered fixed-maximumiteration system(the ordiary system), the input data rate and the number of the bufferrequired is discussed to the buffered-decoder. The performance of the buffered systemand the ordinary system are simulated and compared.(3) Soft decision to the high-order modulation in Rayleigh fading channel isresearched. According to the soft outputs, the performance of LDPC codes decoded byordinary and the buffer system are simulated, based on SC-FDE system. The simulationresults show that the buffered system can achieve good performance while improvingthroughput.