The Optimization Design And Decoder Hardwareimplementation Of QC-LDPC Codes

Low-Density Parity-Check(LDPC) codes are another channel coding which have the performance that close to the Shannon limit. LDPC codes were put forward by Gallager in 1962. However, due to the restriction of the technology at that time, LDPC codes did not get enough attention. Until the late 90’s, the LDPC codes were founded again by encode researchers, and further promoted them. In recent years, because of numerous advantages with its own, LDPC codes become the channel coding scheme of the fourth generation(4G) mobile communication technology, and they are the concern of the people again.Recently, the hardware implementation of encoder and decoder for LDPC codes has drawn the worldwide attentions in channel coding community. Due to the randomness of the parity-check matrix, which bring great difficulty to the hardware implementation. Quasi-Cyclic Low-Density Parity-Check(QC-LDPC) codes, because of its unique characteristics of quasi-cyclic, make it possible for encoding and decoding with a lower complexity. Then, some scholars and experts proposed TDMP algorithm on the basic of TPMP algorithm, and proposed layered decoding algorithm which have being implemented on hardware by the way of layered decoding architecture. Achieving a balance between decoding throughput and hardware resources consumption, the layered decoding architecture has become the mainstream of the decoder structure for QC-LDPC codes.Firstly, we analyse the related knowledge of LDPC and QC-LDPC codes, and focus on constructing QC-LDPC codes with no short circle whose length is equal to 4 based on the multiplicative group of finite fields.Secondly, we analyse emphatically several kinds of soft-decision decoding algorithms of LDPC codes. Through software simulation, the correction factor of normalized min-sum algorithm is identified as 0.8. Then, we compare the error-correction performance of those decoding algorithms. According to the results of the analysis, layered decoding algorithm is chosen for hardware implementation. Finally, we determine the bits of data quantization for hardware implementation as 7.Finally, we use the idea of top-down design to program the decoder with Verilog Hardware Description Language based on Quartus II 9.0 software. Then, the decoder is fit and synthesized on the StratixII familay FPGA devices of Altera. Finally, we do simulation tests by ModelSim 6.4a software. While the maximum iteration of decoder is set as 5, and the operating frequency is set as 35 MHz, the throughput has achieved 92.27 Mbps.