Research Of Data Transfer And Clock Interface Of Front End Electronics In LHAASO WCDA

Research on the large amount of information contained in high energy cosmic ray can help to explore the history of the universe, the evolution of celestial bodies, the environment of space and many other scientific mysteries, through which the model of the origin of the universe can thus be established.Large High Altitude Air Shower Observatory (LHAASO), a large all sky survey system for gamma astronomy with an air shower particle detector array of1km2, is to discover the high energy cosmic ray sources and their evolution, as well as research on dark matter.The Water Cerenkov Detector Array (WCDA) is one of the major components in LHAASO. It consists of4sub-detector arrays. Each of the sub-detector array is a150m×150m water pond with900Photomultiplier tubes (PMTs).Front End Electronics (FEE) is to complete the measurement of charge and time information, and send the outcome to the Data Acquisition system (DAQ).Then the analysis, event reconstruction, and record of the results are done by DAQ.Data transfer and clock interface is an important part of FEE. It is mainly responsible for packaging data of the measurement results based on standard TCP/IP protocol and sending the data to DAQ through the fiber. It also needs to receive the commands from DAQ, and recover the system clock from the serial data stream from the GTX interface.Since there exist3,600channels distributed in the large-scale of90,000m2for the WCDA. It is a good choice to employ a "hardware triggerless" architecture. Compared with conventional trigger systems, the "hardware triggerless" architecture does not need to send the trigger signal back to FEE, so the trigger signal transmission path could be reduced. It can simplify the system structure with multiple nodes scattered in a large area. Meanwhile, a much more flexible trigger system can be achieved based on this triggerless idea. Of course, this architecture imposes higher requirement on data transferring (a high data rate and a good reliability), which is a kernel issue in the design of the WCDA readout electronics.In this dissertation, the data transfer and clock interface is studied. The contents are organized as follows:The first chapter presents the background information of LHAASO, and the requirement for the WCDA readout electronics, as well as its basic structure. In the second chapter, the data transfer and clock distribution methods in several large scale physics experiments are intvestaged, which provides a reference to LHAASO WCDA.In chapter3, the design of the data transfer and clock interface in the WCDA readout electronics is presented. The main content of the chapter includes TCP/IP interface design based on the embedded system, as well as clock recovery and phase adjustment circuit.In chapter4, electronics implementation is introduced. After a brief introduction, detailed information about each part of the circuits are presented.In chapter5, test results are reported, including the functional test and stability test. A data transfer speed more than230Mbps is achieved based on the TCP/IP protocol, beyond the application requirement.In chapter6, conclusion and outlook of the future work are introduced.