Design Of High-speed Data Transfer System Based On PCI Express Interface

With the speed of trains improved constantly, the mobile wireless communication networks on the railway train need to adapt to the high-speed mobile environment. High-speed wireless transmission is bound to make the error rate increase, which leads the decline rate to increase. Therefore, channel parameters need to be quickly tracked in the wireless communication network. Hence, it is important to find the corresponding algorithm to reduce the error rate of the wireless transmission through research and analysis of these parameters.Data transfer system is an important part of data acquisition card which collects and processes high-speed data in the channel. So the high-speed, efficient data transmission scheme is one of the focused and difficulty points for the design of data acquisition card system.The bottleneck of traditional data transmission is one of important factors that hinders the data acquisition card. Therefore, a new interface technology to solve the bottleneck problem of data transmission becomes increasingly prominent. And the emergence of the PCI Express bus lights the future to solve the problem of high-speed data transmission.A design of high-speed data transmission system is proposed here, which is used for the data acquisition card aiming at channel parameters in wireless communication of a high-speed railway. Inaddition this design meets the high-speed and continuous data acquisition. With Verilog HDL that is a kind of hardware description language, the design of modularization, DMA transmission way and using FPGA (Field Programmable Gate Array) to realize the high-speed data transfer. In this thesis there are mainly the following two points.Firstly, this thesis introduces the data acquisition card of the design and the topology and link characteristics of the third generation interconnect bus briefly.Secondly, the whole design scheme of high-speed data transfer system based on PCI Express interface is presented. What's more, the function division and the function of modules are discribed. Then the designs and analyzes are implemented and verified by FPGA. Finally the conclusion is given out.Through simulation and verification, this design is feasible and can meet the performance requirements of data transmission in the high-speed data acquisition card. The design also has some value of application and reference for a universal data acquisition card.