Research Of Encryption And Decryption Algorithms In Trusted Embedded Platform Wlan Transmission Protocol

The development of Wireless Local Area Networks (WLAN) meet the people’s daily life, work and entertainment need, at the same time the WLAN display some security issues. To enhance the WLAN security and reach the enterprise applications standard, China and IEEE put forward their own standards and protocols in WLAN security. China proposed Wireless LAN Authentication and Privacy Infrastructure (WAPI) protocol as the first WLAN security solutions, which now is being widely used in the country. With the respect to the IEEE802.11i protocol, WAPI has been greatly improved in the WLAN Authentication Infrastructure (WAI) and WLAN Privacy Infrastructure (WPI). However, since the security in data transmission is largely determined by the SMS4cipher algorithms, which need large computation and computing resource consumption, improve the efficiency and speed of the SMS4algorithm is important in the process of further development of WAPI protocol.As the SMS4cipher algorithm needs a large amount of computing resources, this paper proposes a way of combining software and hardware to accelerate the SMS4. This method model an Application Specific Instruction Set Processor (ASIP) for SMS4cipher algorithm, design custom instruction set and implement logical structure of the hardware. Firstly, we analyze the logical structure SMS4cipher algorithm and find the algorithm itself can be executed parallelly. Then we further quantify the data flow of the SMS4cipher algorithm to obtain the most commonly instruction cluster. Further we design instructions for all candidate cluster, implement the electronic logical and provide customized instruction set to the software level, so as to accelerate and optimize the SMS4algorithm.In the course of analysis the SMS4algorithm candidate parallel instruction quantitative, the paper presents the SMS4algorithm basic data flow instruction block division method. Firstly, get the data flow graph of SMS4algorithm, and then computing clusters of related DFG converge on the graph, combined with sequential logic and arithmetic algorithms rule, get logically optimized parallel computing clusters. Finally Find optimize parallel computing modules and obtain the valid candidate parallel instructions.To solve the problem of choice candidate instruction, this paper presents two methods which are the Pareto optimal algorithms and0-1knapsack solution to quantify and select the most optimal instructions. By the amount of hardware and the execution cycles which get by our experiments, we can use the Pareto optimal method to get the most optimal condition instructions under a series of different amount of hardware resources. After further logical analysis, we can get the conclusion that the more hardware resources, the more extended instruction can be achieved and the algorithm performs faster. Therefore, the algorithm problem that select the most optimal custom instruction under certain hardware resources can be solved by the0-1knapsack solution.In order to quantitative analysis the SMS4algorithm custom instruction performance and SMS4algorithm optimization, we use the LISA language model a three-stage pipeline MIPS processor and candidate SMS4algorithm custom instruction set. Then use the Verilog to implement the MIPS processor model in FPGA by the electronic system level design approach. Then use the Verilog to implement the MIPS processor model in FPGA by the electronic system level design approach. Experimental results show that the proposed method of extended instruction set for accelerating SMS4algorithms have very good results with a small increase in the hardware execution units to achieve computational speed doubled.