The Research Of Error Control Algorithm Based On NAND Flash

With the growing page capacity of SLC (Single-Level Cell) NAND Flash and the emergence of MLC(Multi-Level Cell) and TLC (Trinary-Level Cell) architecture, the bit error rate of NAND Flash has changed greatly. Traditional Hamming Code ECC (Error Checking and Correcting)can only correct one error and detect two errors.It can not meet the error correction requirement for most of the current NAND Flash anymore.The MLC NAND Flash which is widely used in storage products, it must be use stronger ECC like the binary BCH (Bose Chaudhuri Hoequenghem) Code or the RS (Reed Solomn) Code. The BCH code is a subclass of cyclic code, its error correction ability can control and it is good at dealing with random errors. The RS code is an important subclass of BCH code, it is good at correcting burst errors. In this paper, according to the different page capacity of NAND Flash, we respectively design the error control algorithm with the Hamming code, the binary BCH code and the RS code, using C language to realize the software simulation to verify the correction ability of this ECC codes. The BM (Berlekamp-Massey) iterative algorithm is one of the most important decoding algorithm of BCH code, The details of it and its optimized form are introduced.The research of this paper focuses on the binary BCH code and the RS code. In the Visual C++development platform, an encoding and decoding engine of the binary BCH code and the RS code is implemented, which with different Galois field dimensions, different encoding data length and variable error correction ability.Moreover,using MFC to implement the’Auto Test Tool’for NAND Flash products to do Program/Erase test, an efficient and reliable experiment platform is established. Generally think that the erro of MLC NAND Flash is random and division in each page of the whole NAND Flash.The binary BCH code is considered more suitable for MLC NAND Flash’s error correction because its strong random error correct ability. However,the error model of NAND Flash is not fixed, by summing up, this paper lists3kinds of error model for NAND Flash, namely the ordinary random error model, the multiple bits upset error model and the page error model.According to the multiple bits upset error model, this paper proposes a optimization scheme with RS (178,172) code+RS (145,139) code, it was found that the scheme is better than an binary BCH code which the redundancy rate similar to the optimization scheme. According to the page erro model,if the whole NAND Flash using only one ECC scheme will cause the problem of the NAND Flash’s extra space underutilization, the erro correction for the page is also not ideal,this paper adopts the ’Check Area Share’optimization scheme that use different error correcting ability of binary BCH code schemes to combination.The experimental results show that both the resource utilization and the error correction performance are improved.