| A revolutionary of the high-speed data transmission technology is led to by the rapiddevelopment of computer technology and signal processing techniques.The transmissionrate of USB is leading in the development of the promotion of the Power Management,thehumanoid Allocation of resources and so on,which is from1.2Mb/s to5Gb/s in only20years.The High-speed data transmission system based on the USB3.0arises because of thetransport Interface USB2.0can‘t meet the request of test in the new concept of dynamictesting which advanced the higher demand of storage capacity and transmissionrate.Presently,the research of the high-speed data transmission system based on the USB3.0is in the stage of design.However,there are some problem needed to be handled as theexploitation of drives,the communication between interfaces and FPGA,signals of thePCB,the integrity of power and so on.In the study,the Cadence is used to draw schematicsand PCB which is also used to emulate signals,in order to solve the problem of theinterference,the reflex and the integrity of the power. The following aspects of this paperare proposed:1. Several key issues that USB2.0interface encountered in the application aresummarized; make a more effective solution and the simulation;2. A feasible scheme is designed and drawed by comparing the function ofhigh-speed interfaces and summarizing superiorities of USB3.0;3. The Cadence complete schematics of the high-speed data transmissionsystem,bringing the connection of FPGA and DDRII.Which also solves the problem of theinterference,the reflex,the differential Line design and the integrity of the power accordingto emulates signals,completing the PCB design of the high-speed data transmission system; 4. The system firmware and FPGA logic control timing is designed, and simulatedwhen GPIF II interface to work in the SLAVE FIFO mode, firmware framework has beenimproved and implemented to communicate with the FPGA;5. Some testing of the system is completed, such as the hardware, speed, direction oftransmission, and the feasibility of the system is verified. |