A Study On The Least Mean Square Calibration Algorithm For The Pipelined ADC

With the development of calibration for pipelined ADC(Analog to Digital Conversion),the digital background calibration for pipelined ADC based on LMS (Least MeanSquare)algorithm has become a research hotspot due to its advantages. However, chipintegration is still a problem, and domestic reports show that exploration on this is still restingon simulation. Therefore this thesis will calibrate the pipelined ADC with a slow but accurateADC and LMS algorithm on board level to improve the performance of pipelined ADC. Atlast, optimization of the algorithm to reduce the calibration time is proposed.In this study, the validation of LMS calibrating pipelined ADC focuses on three aspects,simulation on Matlab, Verilog programming and calibration on board. Firstly, in order tovalidate the effectiveness of the model, the model and simulation of calibrating pipelined ADCbased on LMS algorithm was developed. The results show that the Effective Number OfBits(ENOB)can be improved from8.07bit to12.19bit, the Spurious Free DynamicRange(SFDR) increased from56.73dB to83.99dB and the Signal To Noise Ratio(SNR)can beimproved from50.31dB to75.15dB. Secondly, in order to verify the effectiveness of theVerilog programming,in order to reduce the iteration error, adjust the step size, the iterationerror is in the range of35at last. Then the code was downloaded in the EP4CE22F17C6board，the results indicate that the ENOB, SFDR and SNR can be all improved from12.77bit,80.71dB and78.65dB to13.64bit,99.21dB and83.87dB, respectively. Finally, in order to verifythe effectiveness of calibration for ADC which was designed by our laboratory, testing of thecalibrating system has been carried out, which turned out that the ENOB, SFDR and SNRcould be all improved from9.9bit,80.68dB and61.37dB before calibration to10.39,83.65dBand64.29dBafter calibration, respectively.Based on the above, the Variable Step Size LMS algorithm based on S function (SVSLMSalgorithm) was simulated with Matlab so that less calibration time could be obtained, thesimulation results manifest that the iterations of SVSLMS is a half of that of the LMS with thesame input signal and reference input signal, thus,50%of time could be saved compared toconventional methodologies.The work in this thesis could be as a reference for improving the performance of pipelined ADC and integrating the calibrating algorithm on a chip.