The Design Of TLD In Hign Performance Embedded CPU

With the increasingly wide use of embedded microprocessor in production and all aspects of life,performance and power consumption have become important indicators of embedded microprocessor design. Translation look-aside buffer (TLB) has an important role in these two indicators on the embedded microprocessor, so the study of TLB in embedded processor design is very important. This thesis is based on Hangzhou Zhongtian Microsystems CK510series which are high-performance embedded processors and its simulation platform and focuses on high-performance embedded processor’s TLB unit. The main contents of this thesis and innovations are as the followings:1. Proposed a two-stage TLB architecture with consecutive page merging and recycling. Based on the locality features of continuous page allocation and the analyzing of the behavior of the benchmark, this thesis proposes a two-stage TLB architecture with consecutive page merging and recycling for high-performance embedded processors. Based on two-way set associative Main TLB, the main idea of this method is to design Recycling TLB (RTLB) for consecutive page merging and recycling which can recycle the old replaced entry caused by the conflict of two-way associative main TLB. Meanwhile, RTLB can also merge two consecutive pages. Thus this old entry can get quickly as there is no need of getting it from page table if it should be used in the future. Using some applications in EEMBC, the experiment result shows that the missing ration of TLB in this thesis decreases. As to the replacement strategy of RTLB, this thesis chooses LRU and FIFO. Both of the two strategies’hardware implementations are described in detail. Meanwhile the two different replacement policy and different number of entries are studied experimentally.2. Proposed a hardware refill mechanism based on consecutive page merging and PTE base address caching. The analysis of TLB access time shows that hardware refill time is a large portion of the total TLB accessing time. Thus this thesis proposes two methods to shorten the hardware refill time, namely:a) merging two entries whose VPN and PPN are both consecutive in Main TLB during hardware refill, which can expand the Main TLB’s capacity, reduce TLB miss rate and reduce hardware refill times.b) Caching the page table entry (PTE) base address getting from the first query to the page table. So the VPNs whose PTE base addresses are the same will not need to access page table to get PTE base address, which can save half of the hardware refill time. These two methods can improve the performance of TLB from reducing the number of hardware refill and shortening the time of a single hardware refill respectively. Using some applications in EEMBC, the experiment result shows that the hardware refill mechanisms in the thesis can reduce total TLB accessing time significantly compared to traditional TLB.