Research And Implementation Of Cache Optimization Of Shenwei Processor Page Table Structure

Solution of the "memory wall problem" caused by the increasing gap between the performance of main memory and the performance of microprocessors is a problem that is constantly explored in the development of microprocessors.By setting the Cache,the use of hierarchical storage structure is one of the technologies commonly used by modern microprocessors.The translation of virtual and real addresses is generally on the critical path of Cache access.Modern microprocessors will use memory management unit(MMU)hardware to implement paged storage management,and bypass conversion buffer(TLB)to increase the speed of virtual and real address replacement;Therefore,the optimized design of the memory management unit plays a vital role in improving the overall performance of the microprocessor.As the scale of applications grows larger,the page table space required by the microprocessor also increases.The use of multi-level page tables effectively alleviates the problem of page table space,but it also increases the processing overhead when the TLB is not hit,this overhead consumes a lot of processor runtime and reduces processor performance.Analyzing the factors that affect performance,by selecting appropriate parameters and choosing the appropriate memory management unit Cache(MMU Cache)according to the microstructure of different microprocessors,is an effective way to reduce the processing overhead of TLB miss hardware.Therefore,a properly designed memory management unit buffer is also essential to the microprocessor.This paper takes the new generation server processor of Shenwei processor as the research object,designs the appropriate page table structure buffer,combines the page table structure buffer to optimize the design of MMU management,and proposes and implements a hardware query based on state machine control Automatic page table and active TLB loading method.In this paper,through in-depth research on the structure,working principle and performance influencing factors of the memory management unit and MMU Cache,the focus is on analyzing the impact of its various parameters on the design;Through consideration of factors such as application environment,cost and power consumption,an emulator is used for experimental testing,and the design parameters of the page table structure buffer are determined according to data analysis,and the optimization method and circuit design of the page table structure buffer and MMU are determined;Through the specific implementation of RTL code,and then perform RTL-level functional simulation to verify the correctness and preliminary performance evaluation of the design module;finally,through the hardware overhead evaluation to determine the feasibility of the design in the chip.According to the experimental results,this paper adopts a two-level page table structure buffer,uses 4-entry PGD Cache and 32-entry PMD Cache,and uses LRU replacement algorithm to achieve a higher hit rate of 97.55%and 99.53%and less hardware overhead.The simulation proves the correctness and feasibility of the function of the circuit design,which is improved compared with the previous generation Shenwei processor.