Performance Optimization Of Memory Control Systems

In recent years, with the increasing of the processor's frequency and the parallel degrees in processor's instruction executing, the processor's memory access operations expand greatly and bring great pressure to computer systems. However, contrast to the performance improvement of processor, the performance of memory improves very slowly, that causes the latency of memory access becomes the major bottleneck of the performance improvement for the modern computer systems. In order to improve the performance of computer systems, it is essential to optimize the performance of memory control systems.From the point of view of decreasing the latency of memory access and increasing the bandwidth of memory access, combined with the characteristics of Goodson-2 processor's memory access action when Goodson-2 processor running SPEC CPU2000 test programs, several approaches that can bring performance improvement of system's memory access is proposed in this dissertation. The detailed research improvements are as follows.1. Utilizing the characteristics that all of the modern DRAM devices can support two page strategies (Close page mode and Open page mode) and the banks in DRAM can be accessed concurrently, and based on the spatial locality characters of Goodson-2 processor's memory accesses operations obtained while Goodson-2 processor running the SPEC CPU2000 test programs, a dynamic page strategy is proposed in this dissertation.2. A prefetching policy in memory control system is proposed, which uses the idea of stream buffer proposed by Jouppi. In the prefetching policy proposed in this dissertation, the memory access stream is allocated based on the spatial locality characters of Goodson-2 processor's memory accesses operations when Goodson-2 processor running SPEC CPU2000 test programs. In the implementation of prefetching, the prefetching operation is managed by utilizing the information that the dynamic page management circuits provided, so the prefetching policy in this dissertation can reduce the negative affect on memory access bandwidth contrast to the prefetching in processors.3. Combined with the characters of system bus used in the Goodson-2 processor, we design a write buffer in Goodson-2 memory control system in order to improve the processor's memory access bandwidth.4. In order to improve the bandwidth of system bus, we propose a system bus protocol that utilizes the split transaction technology and adopts the protocol used in current Goodson-2 processor's system bus. The new system bus protocol proposed in this dissertation uses concise handshake policy to guarantee multi-read operations can be transferred on the system bus discretely.