Embedded Memory Management Unit Low Power Technique Research And Design

With the rapid development of embedded microprocessor technology and the extensive use of portable electronic devices, power consumption has become one of the main challenges of embedded design. Memory management unit (MMU), implemented in hardware to realize virtual memory technique, is major concern of power consumption of embedded processors. This thesis focuses on the study and design about the low-power technology of embedded memory management unit, especially the TLB low-power design technology. The thesis proposes two TLB low-power technologies with the fully-synthesis two-level TLB architecture. The main content and original contributions of this thesis are as follows:1. A two-level TLB low-power design based on predict buffer. This thesis proposed the new TLB low power design method based on memory access locality principle. Between the two level TLBs, an independent and hardware configurable prediction buffer was introduced to dynamically predict the access sequences of the second level TLB, which could reduce its access penalty when the first level TLB missed and significantly reduce the dynamic power consumption with little control logic. Experiment shows that compared with the traditional two-level TLB structure, the average access cycles of the second level TLB are just about 20% of the traditional one, at a cost of only 1.81% area increment, which support low power and low cost embedded application.2. An uTLB low-power design based on historical access information prediction. By using the history access information register (HR) to dynamically record and readjust the history access information, the physical frame number could be fetched directly from the last access result. This method could effectively reduce the times of paralleled comparisons of the full associative uTLB entrys. Meanwhile, there also proposed the LRU replacement policy of uTLB that improved by clock gating techniques, be able to eliminate swing power of the LRU matrix. Experiment shows that compared with the traditional uTLB, the average times of paralleled comparisons of the uTLB are just about 62% of the traditional one. Techniques proposed in this thesis facilitate the implementation of embedded processor, and have positive effects on transition speed and power of and embedded memory management unit, and have little hardware cost.